The latest release features:
- Support for multi-cluster architectures. The clusters can be organized as either sharing an inter-cluster communication bus or a mesh point-to-point operand network.
- Support for application-specific instruction-set extensions.
- Support for automatic vectorization .
- Support for Fortran applications via a SUIF to Trimaran translator.
- Advanced simulation of the memory system using the M5 simulator.
- Code generation infrastructure to handle ISAs with arbitrary literal bit-width constraints.
- Code generation for the ARM ISA.
- New datatype attribute associated with every operand to describe the data type (integer/float/predicate), whether the operand is signed or unsigned, and the operand bit-width.
- Support for the long long datatype.
- Register allocation has been completely rewritten and many optimizations have been added to the default path.
- Significantly improved code quality.
- Lots of bug fixes.
- A new comprehensive manual.
This frontend implements a set of SUIF passes that convert SUIF IR to Trimaran IR (lcode). This add-on combines SUIF high level program analysis passes with the Trimaran compiler and its rich collection of machine specific optimizations. Sam Larsen's doctoral works demonstrates the value of combining frontend program analysis and backend machine optimizations in the context of automatic vectorization.
are making available a snapshot release of Trimaran (v.3.7)
that includes more accurate tracking of the memory system
performance. This release is being made available due to
There are various other features that were added (and bugs fixes) but not documented here. This release does pass our regression test suite and is fairly stable. A new Trimaran distribution will also be made available soon which will include support for clustered architectures.
Note that as with all memory simulations, there are various details that are hard to simulate and you should understand the simulation infrastructure before reporting numbers for publications when memory simulation is enabled. The current distribution also includes the cache simulation interface from SimpleScalar for those who wish to use it (this interface is activated via a compile time flag in the trimaran/simu/src/emulib/Makefile).
This snapshot release also includes more statistics tracking and a new format of the simulator output files. Note however that this new output is not compatible with the GUI visualization tools.
You can reach other researchers that are using Trimaran by writing to trimaran-users at trimaran.org. Note: the mailing list is no longer live..
The latest version of Trimaran (v.3.1.b) is compatible with GCC 3.3.x.
The latest version of Trimaran (v.3.0.b) includes an interface to the Dinero IV cache simulator. It also includes a fast new simulation environment, and it is compatible with GCC 3.1.x.
Triceps is an ARM Code Generator now packaged with Trimaran. This a beta release version and incremental updates will be released as they become available.
HPL-PD Architecture Specification-Version 1.1 is now available.
Trimaran 2.0 is now available. It supports all of the SPEC CINT95 benchmarks as well as a variety of SPEC CPU92 benchmarks, digital and mediabench applications.