The following presents a brief overview of Trimaran. A more elaborate overview appears in Lecture Notes in Computer Science.

Trimaran is an integrated compiler and simulation infrastructure for research in computer architecture and compiler optimizations. Trimaran is highly parameterizable, and can target a wide range of architectures that embody embedded processors, high-end VLIW processors, and multi-clustered architectures. Trimaran also facilitates the exploration of the architecture design space, and is well suited for the automatic synthesis of programmable application specific architectures. It allows for customization of all aspects of an architecture, including the datapath, control path, instruction set, interconnect, and instruction/data memory subsystems.

The modular nature of the compiler and the hierarchical intermediate program representation used throughout makes the construction and insertion of new compilation modules into the compiler especially easy. Trimaran is already populated with a large number of existing compilation modules, providing leverage for new compiler research as well as education in advanced compiler topics. The Trimaran Graphical User Interface (GUI) makes the configuration and use of the system surprisingly easy.

Among the rich suite of compiler analysis and optimizations are:

• Advanced region formation algorithms (e.g., superblocks and hyperblocks) to expose instruction level parallelism with speculation and predication.
• Various backend instruction partitioning and mapping algorithms for automatically distributing parallelism in a multi-clustered architecture.
• A first of its kind backend vectorizer that extracts and exploits data level parallelism using short vector instructions (SIMD).
• Various register allocation heuristics.
• Instruction scheduling algorithms including software pipelining with modulo scheduling.

Although there are several compiler infrastructures available to the research community, Trimaran is unique in that it is especially geared toward compiler and architecture research. Trimaran is used for designing, implementing, and testing new optimizations, as well as the evaluation of various architectural innovations. Trimaran is also widely used for teaching and education purposes at several universities worldwide.

We are committed to releasing a robust, tested, and documented system. Our website (http://www.trimaran.org) provides the latest information on Trimaran, and includes links to download the system, as well as documentation and other useful resources.

The following is a summary of the newest Trimaran features made available in an current release (dated 12/16/2007).

• Support for multi-cluster architectures. The clusters can be organized as either sharing an inter-cluster communication bus or a mesh point-to-point operand network.
• Support for application-specific instruction-set extensions.
• Support for automatic vectorization.
• Support for Fortran applications via a SUIF to Trimaran translator.
• Advanced simulation of the memory system using the M5 simulator.
• Code generation infrastructure to handle ISAs with arbitrary literal bit-width constraints.
• Code generation for the ARM ISA.
• New datatype attribute associated with every operand to describe the data type (integer/float/predicate), whether the operand is signed or unsigned, and the operand bit-width.
• Support for the long long datatype.
• Register allocation has been completely rewritten and many optimizations have been added to the default path.
• Significantly improved code quality.
• Lots of bug fixes.